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rev. 1.1 1/13 copyright ? 2013 by silicon laboratories SI510/511 SI510/511 c rystal o scillator (xo) 100 kh z to 250 mh z features applications description the SI510/511 xo utilizes silicon laboratories' advanced dspll technology to provide any frequency from 100 khz to 250 mhz. unlike a traditional xo where a different crystal is required for each output frequency, the SI510/511 uses one fixed crystal and silicon labs? proprietary dspll synthesizer to generate any frequency across this range. this ic-based approach allows the crystal resonator to provide enhanced reliability, improved mechanical robustness, and excellent stability. in addition, this solution provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. crystal esr and dld are individually production-tested to guarantee performance and enhance reliability. the SI510/511 is factory- configurable for a wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability. specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators. functional block diagram ? supports any frequency from 100 khz to 250 mhz ? low jitter operation ? 2 to 4 week lead times ? total stability includes 10-year aging ? comprehensive production test coverage includes crystal esr and dld ? on-chip ldo regulator for power supply noise filtering ? 3.3, 2.5, or 1.8 v operation ? differential (lvpecl, lvds, hcsl) or cmos output options ? optional integrated 1:2 cmos fanout buffer ? runt suppression on oe and power on ? industry standard 5 x 7 and 3.2x5 mm packages ? pb-free, rohs compliant ? ?40 to 85 o c operation ? sonet/sdh/otn ? gigabit ethernet ? fibre channel/sas/sata ? pci express ? 3g-sdi/hd-sdi/sdi ? te l e c o m ? switches/routers ? fpga/asic clock generation v dd any-frequency 0.1 to 250 mhz dspll ? synthesis fixed frequency oscillator clk+ clk? oe gnd low noise regulator ordering information: see page 14. pin assignments: see page 12. si5602 1 2 3 6 5 4 gnd oe v dd clk+ clk? nc 1 2 3 6 5 4 gnd nc v dd clk+ clk? oe SI510(lvds/lvpecl/hcsl/ dual cmos) SI510 (cmos) si511(lvds/lvpecl/hcsl/ dual cmos) 1 2 4 3 gnd v dd clk oe 1 2 3 6 5 4 gnd nc v dd clk+ clk? oe free datasheet http:///
SI510/511 2 rev. 1.1 free datasheet http:///
SI510/511 rev. 1.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1. dual cmos buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4. SI510/511 mark specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. package outline diagram: 5 x 7 mm, 4-pi n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. pcb land pattern: 5 x 7 mm, 4- pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 7. package outline diagram: 5 x 7 mm, 6-pi n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. pcb land pattern: 5 x 7 mm, 6- pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 9. package outline diagram: 3. 2 x 5 mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10. pcb land pattern: 3.2x5mm, 4-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11. package outline diagram: 3.2 x 5 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12. pcb land pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 free datasheet http:///
SI510/511 4 rev. 1.1 1. electrical specifications table 1. operating specifications v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max unit supply voltage v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 v 1.8 v option 1.71 1.8 1.89 v supply current i dd cmos, 100 mhz, single-ended ?21 26ma lvds (output enabled) ?19 23ma lvpecl (output enabled) ?39 43ma hcsl (output enabled) ?41 44ma tristate (output disabled) ?? 18ma oe "1" setting v ih see note 0.80 x v dd ??v oe "0" setting v il see note ? ? 0.20 x v dd v oe internal pull-up/pull- down resistor * r i ?45 ?k ? operating temperature t a ?40 ? 85 o c *note: active high and active low polarity oe options avail able. active high option includes an internal pull-up. active low option includes an internal pull-down. see ordering information on page 14. free datasheet http:///
SI510/511 rev. 1.1 5 table 2. output clock frequency characteristics v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max unit nominal frequency f o cmos, dual cmos 0.1 ? 212.5 mhz f o lvds/lvpecl/hcsl 0.1 ? 250 mhz total stability* frequency stability grade c ?30 ? +30 ppm frequency stability grade b ?50 ? +50 ppm frequency stability grade a ?100 ? +100 ppm temperature stability frequency stability grade c ?20 ? +20 ppm frequency stability grade b ?25 ? +25 ppm frequency stability grade a ?50 ? +50 ppm startup time t su minimum v dd until output frequency (f o ) within specification ??10ms disable time t d f o ? 10 mhz ? ? 5 s f o <10mhz ? ? 40 s enable time t e f o ? 10 mhz ? ? 20 s f o <10mhz ? ? 60 s *note: total stability includes initial accuracy, operating temperature, supply voltage c hange, load change, shock and vibration (not under operation), and 10 years aging at 40 o c. free datasheet http:///
SI510/511 6 rev. 1.1 table 3. output clock levels and symmetry v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max unit cmos output logic high v oh 0.85 x v dd ??v cmos output logic low v ol ? ? 0.15 x v dd v cmos output logic high drive i oh 3.3 v ?8 ? ? ma 2.5 v ?6 ? ? ma 1.8 v ?4 ? ? ma cmos output logic low drive i ol 3.3 v 8 ? ? ma 2.5 v 6 ? ? ma 1.8 v 4 ? ? ma cmos output rise/fall time (20 to 80% v dd ) t r /t f 0.1 to 212.5 mhz, c l = 15 pf ?0.81.2ns 0.1 to 212.5 mhz, c l = no load ?0.60.9ns lvpecl/hcsl output rise/fall time (20 to 80% vdd) t r /t f ??565ps lvds output rise/fall time (20 to 80% vdd) t r /t f ??800ps lvpecl output common mode v oc 50 ? to v dd ? 2 v, single-ended ?v dd ? 1.4 v ?v lvpecl output swing v o 50 ? to v dd ? 2 v, single-ended 0.55 0.8 0.90 v ppse lvds output common mode v oc 100 ? line-line v dd = 3.3/2.5 v 1.13 1.23 1.33 v 100 ? line-line, v dd = 1.8 v 0.83 0.92 1.00 v lvds output swing v o single-ended, 100 ?? differential termination 0.25 0.35 0.45 v ppse hcsl output common mode v oc 50 ?? to ground 0.35 0.38 0.42 v hcsl output swing v o single-ended 0.58 0.73 0.85 v ppse duty cycle dc all formats 485052% free datasheet http:///
SI510/511 rev. 1.1 7 table 4. output clock jitter and phase noise (lvpecl) v dd = 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = lvpecl parameter symbol test condition min typ max unit period jitter (rms) jprms 10k samples 1 ??1.3ps period jitter (pk-pk) jppkpk 10k samples 1 ??11ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.310.5 ps 12 khz to 20 mhz integration band- width 2 (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??86?dbc/hz 1 khz ? ?109 ? dbc/hz 10 khz ? ?116 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz additive rms jitter due to external power supply noise 3 jpsr 10 khz sinusoidal noise ? 3.0 ? ps 100 khz sinusoidal noise ? 3.5 ? ps 500 khz sinusoidal noise ? 3.5 ? ps 1 mhz sinusoidal noise ? 3.5 ? ps spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 mhz. 2. applies to output frequencies: 100 , 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 mhz. 3. 156.25 mhz. increase in jitter on output clock due to sinewave noise added to vdd (2.5/3.3 v = 100 mvpp). free datasheet http:///
SI510/511 8 rev. 1.1 table 5. output clock jitter and phase noise (lvds) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = lvds parameter symbol test condition min typ max unit period jitter (rms) jprms 10k samples 1 ??2.1ps period jitter (pk-pk) jppkpk 10k samples 1 ??18ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.250.55ps 12 khz to 20 mhz integration band- width 2 (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??86?dbc/hz 1 khz ? ?109 ? dbc/hz 10 khz ? ?116 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 mhz. 2. applies to output frequencies: 100 , 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 mhz. free datasheet http:///
SI510/511 rev. 1.1 9 table 6. output clock jitter and phase noise (hcsl) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = hcsl parameter symbol test condition min typ max unit period jitter (rms) jprms 10k samples * ??1.2ps period jitter (pk-pk) jppkpk 10k samples * ??11ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth * (brickwall) ?0.250.30ps 12 khz to 20 mhz integration band- width * (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??90?dbc/hz 1khz ? ?112 ? dbc/hz 10 khz ? ?120 ? dbc/hz 100 khz ? ?127 ? dbc/hz 1 mhz ? ?140 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc *note: applies to an output frequency of 100 mhz. free datasheet http:///
SI510/511 10 rev. 1.1 table 7. output clock jitter and phase noise (cmos, dual cmos) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = cmos, dual cmos parameter symbol test condition min typ max unit phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.250.35ps 12 khz to 20 mhz integration band- width 2 (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??86?dbc/hz 1 khz ? ?108 ? dbc/hz 10 khz ? ?115 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 mhz. 2. applies to output frequencies: 100, 106.25, 1 25, 148.35165, 148.5, 150, 15 5.52, 156.25, 212.5 mhz. table 8. environmental compliance and package information parameter conditions/test method mechanical shock mil-std-883, method 2002 mechanical vibration mil-std-883, method 2007 solderability mil-std-883, method 2003 gross and fine leak mil-std-883, method 1014 resistance to solder heat mil-std-883, method 2036 moisture sensitivity level msl 1 contact pads gold over nickel free datasheet http:///
SI510/511 rev. 1.1 11 table 9. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 110 c/w table 10. absolute maximum ratings 1 parameter symbol rating unit maximum operating temperature t amax 85 o c storage temperature t s ?55 to +125 o c supply voltage v dd ?0.5 to +3.8 v input voltage (any input pin) v i ?0.5 to v dd + 0.3 v esd sensitivity (hbm, per jesd22-a114) hbm 2 kv soldering temperature (pb-free profile) 2 t peak 260 o c soldering temperature time at t peak (pb-free profile) 2 t p 20?40 sec notes: 1. stresses beyond those listed in this table may cause pe rmanent damage to the device. functional operation or specification compliance is not impli ed at these conditions. exposure to ma ximum rating conditions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020. free datasheet http:///
SI510/511 12 rev. 1.1 2. pin descriptions *supports integrated 1:2 cmos buffer. see orderin g information and section 2.1?dual cmos buffer?. table 11. SI510 pin descriptions (cmos) pin name cmos function 1 oe output enable. includes internal pull-up for oe active high. includes internal pull-down for oe active low. see ordering information. 2 gnd electrical and case ground. 3 clk clock output. 4 v dd power supply voltage. table 12. SI510 pin descriptions (lvpecl/lvds/hcsl, dual cmos, oe pin 2) pin name lvpecl/lvds/hcsl function 1 nc no connect. make no external connection to this pin. 2 oe output enable. includes internal pull-up for oe active high. includes internal pull-down for oe active low. see ordering information. 3 gnd electrical and case ground. 4 clk+ clock output. 5 clk? complementary clock output. 6 v dd power supply voltage. table 13. si511 pin descriptions (lvpecl/lvds/hcsl, dual cmos, oe pin 1) pin name lvpecl/lvds/hcsl function 1 oe output enable. includes internal pu ll-up for oe active high. includes internal pull-down for oe active low. see ordering information. 2 nc no connect. make no external connection to this pin. 3 gnd electrical and case ground. 4 clk+ clock output. 5 clk? complementary clock output. 6 v dd power supply voltage. 1 2 3 6 5 4 gnd oe v dd clk+ clk?* nc 1 2 3 6 5 4 gnd nc v dd clk+ clk?* oe SI510 (cmos) SI510 (lvds/lvpecl/hcsl/dual cmos*) si511 (lvds/lvpecl/hcsl/dualcmos)*) 1 2 4 3 gnd v dd clk oe free datasheet http:///
SI510/511 rev. 1.1 13 2.1. dual cmos buffer dual cmos output format ordering options support either complementary or in-phase output signals. this feature enables replacement of multiple xos with a single SI510/11 device. figure 1. integrated 1:2 cmos buffer supports complementary or in-phase outputs ~ ~ complementary outputs in-phase outputs free datasheet http:///
SI510/511 14 rev. 1.1 3. ordering information the SI510/511 supports a wide variet y of options including frequency, stability, output format, and v dd . specific device configurations are programmed into the SI510/511 at time of shipment. configurations can be specified using the part number conf iguration chart below. silicon labs pr ovides a web browse r-based part number configuration utility to simplif y this process. refer to www.silabs.com/vcxopartnumber to access this tool. the SI510/511 xo series is supplied in industry-standard, rohs compliant, lead-free, 3.2 x 5.0 mm and 5 x 7 mm packages. tape and reel packaging is an ordering option. figure 2. part number syntax example orderable part numb er: 510ecb156m250aag supports 2.5 v lvpecl, 30 ppm total stability, oe active low in 5 x 7 mm package across ?40 o c to 85 o c temperature range. the output frequency is 156.25 mhz. note: cmos and dual cmos maximum frequency is 212.5 mhz. a = revision: a g = temp range: -40c to 85c r = tape & reel; blank = trays. series output format oe pin package 510 cmos oe on pin 1 4-pin 510 lvpecl, lvds, hcsl, dual cmos oe on pin 2 6-pin 511 lvpecl, lvds, hcsl, dual cmos oe on pin 1 6-pin x x agr 51x x xxxmxxx x 1 st option code: output format vdd output format x x agr 51x x xxxmxxx x vdd output format a 3.3v lvpecl b3.3v lvds c3.3v cmos d 33v hcsl 3 rd option code: output enable oe polarity a oe active high package option dimensions a 5x7mm d 3 . 3v hcsl e 2.5v lvpecl f2.5v lvds g2.5v cmos h 25v hcsl a oe active high b oe active low 2 nd option code: frequency stability a 5 x 7 mm b 3.2 x 5 mm h 2 . 5v hcsl j1.8v lvds k1.8v cmos l 1.8v hcsl m 33v dlcmos(i h) frequency code f diti frequency stability total temperature a 100ppm 50ppm b 50pp m2 5pp m m 3 . 3v d ua l cmos (i n-p h ase ) n 3.3v dual cmos (complementary) p 2.5v dual cmos (in-phase) q 2.5v dual cmos (complementary) f requency d escr i p ti on mxxxxxx f out < 1 mhz xmxxxxx 1 mhz ? f out < 10 mhz xxmxxxx 10 mhz ? f out < 100 mhz 50pp 5pp c 30ppm 20ppm r1.8 v dual cmos (in-phase) s 1.8v dual cmos (complementary) xxxmxxx 100 mhz ? f out < 250 mhz xxxxxx code if frequency requires >6 digit resolution free datasheet http:///
SI510/511 rev. 1.1 15 4. SI510/511 mark specification figure 3 illustrates the mark sp ecification for the SI510/511. use the pa rt number configuratio n utility located at: www.silabs.com/vcxopartnumber to cross-reference the mark code to a specific device configuration. figure 3. top mark 0ccccc ttt t t t yy 0 = SI510, 1 = si511 ccccc = mark code tttttt = assembly manufacturing code yy = year ww = work week ww free datasheet http:///
SI510/511 16 rev. 1.1 5. package outline di agram: 5x7mm, 4-pin figure 4 illustrates the package details for the 5 x 7 mm si 510/511. table 14 lists the values for the dimensions shown in the illustration. figure 4. SI510/511 outline diagram table 14. package diagram dimensions (mm) dimension min nom max a 1.50 1.65 1.80 b 1.30 1.40 1.50 c 0.50 0.60 0.70 d 5.00 bsc d1 4.30 4.40 4.50 e 5.08 bsc f0.50 typ e 7.00 bsc e1 6.10 6.20 6.30 h 0.55 0.65 0.75 l 1.17 1.27 1.37 l1 0.05 0.10 0.15 p 2.50 2.60 2.70 aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ? free datasheet http:///
SI510/511 rev. 1.1 17 6. pcb land pattern: 5 x 7 mm, 4-pin figure 5 illustrates the 5 x 7 mm pcb land pattern for the 5 x 7 mm SI510/511. table 15 lists the values for the dimensions shown in the illustration. figure 5. SI510/511 pcb land pattern table 15. pcb land pattern dimensions (mm) dimension (mm) c1 4.20 e5.08 x1 1.55 y1 1.95 notes: general 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum materi al condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearanc e between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020d specification for small body components. ? free datasheet http:///
SI510/511 18 rev. 1.1 7. package outline di agram: 5x7mm, 6-pin figure 6 illustrates the package details fo r the SI510/511. table 16 lists the val ues for the dimensio ns shown in the illustration. figure 6. SI510/511 outline diagram table 16. package diagram dimensions (mm) dimension min nom max a 1.50 1.65 1.80 b 1.30 1.40 1.50 c 0.50 0.60 0.70 d 5.00 bsc d1 4.30 4.40 4.50 e 2.54 bsc e 7.00 bsc e1 6.10 6.20 6.30 h 0.55 0.65 0.75 l 1.17 1.27 1.37 l1 0.05 0.10 0.15 p 1.80 ? 2.60 r0.70 ref aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ? free datasheet http:///
SI510/511 rev. 1.1 19 8. pcb land pattern: 5 x 7 mm, 6-pin figure 7 illustrates the 5 x 7 mm pcb land pattern for the SI510/511. table 17 lists the values for the dimensions shown in the illustration. figure 7. SI510/511 pcb land pattern table 17. pcb land pattern dimensions (mm) dimension (mm) c1 4.20 e2.54 x1 1.55 y1 1.95 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is bas ed on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per th e jedec/ipc j-std-020 specification for small body components. free datasheet http:///
SI510/511 20 rev. 1.1 9. package outline di agram: 3.2 x 5 mm, 4-pin figure 8 illustrates the package details for the 3.2 x 5 mm si 510/511. table 18 lists the values for the dimensions shown in the illustration. figure 8. SI510/511 outline diagram table 18. package diagram dimensions (mm) dimension min nom max a 1.06 1.17 1.28 b 1.10 1.20 1.30 c 0.70 0.80 0.90 d3.20 bsc d1 2.55 2.60 2.65 e2.54 bsc f0.40 typ e5.00 bsc e1 4.35 4.40 4.45 h 0.40 0.50 0.60 l 0.90 1.00 1.10 l1 0.05 0.10 0.15 p 1.17 1.27 1.37 aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ? free datasheet http:///
SI510/511 rev. 1.1 21 10. pcb land pattern: 3.2 x 5 mm, 4-pin figure 9 illustrates the 3.2 x 5 mm pcb land pattern for the SI510/511. table 19 lists the values for the dimensions shown in the illustration. figure 9. SI510/511 pcb land pattern table 19. pcb land pattern dimensions (mm) dimension (mm) c1 2.60 e2.54 x1 1.35 y1 1.70 notes: general 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-po lished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is pe r the jedec/ipc j-std- 020 specification for small body components. free datasheet http:///
SI510/511 22 rev. 1.1 11. package outline di agram: 3.2 x 5 mm, 6-pin figure 10 illustrates the package details for the 3.2 x 5 mm SI510/511. table 20 lists the values for the dimensions shown in the illustration. figure 10. SI510/511 outline diagram table 20. package diagram dimensions (mm) dimension min nom max a1.061.171.28 b0.540.640.74 c0.350.450.55 d 3.20 bsc d1 2.55 2.60 2.65 e 1.27 bsc e 5.00 bsc e1 4.35 4.40 4.45 h0.450.550.65 l0.901.001.10 l1 0.05 0.10 0.15 p1.171.271.37 r0.32 ref aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ? free datasheet http:///
SI510/511 rev. 1.1 23 12. pcb land pattern: 3.2 x 5.0 mm, 6-pin figure 11 illustrates the 3.2 x 5.0 mm pc b land pattern for the SI510/511. table 21 lists the values for the dimensions shown in the illustration. figure 11. SI510/511 recommended pcb land pattern table 21. pcb land pattern dimensions (mm) dimension (mm) c1 2.60 e1.27 x1 0.80 y1 1.70 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-199 4 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polis hed stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std- 020c specification for small body components. ? free datasheet http:///
SI510/511 24 rev. 1.1 d ocument c hange l ist revision 0.9 to revision 1.0 ? updated table 1 on page 4. ?? updates to supply current typical and maximum values for cmos, lvds, lvpecl and hcsl. ?? cmos frequency test condition corrected to 100 mhz. ?? updates to oe vih minimum and vil maximum values. ? updated table 2 on page 5. ?? dual cmos nominal frequency maximum added. ?? total stability footnotes clarified for 10 year aging at 40 c. ?? disable time maximum values updated. ?? enable time parameter added. ? updated table 3 on page 6. ?? cmos output rise / fall time typical and maximum values updated. ?? lvpecl/hcsl output rise / fall time maximum value updated. ?? lvpecl output swing maximum value updated. ?? lvds output common mode typical and maximum values updated. ?? hcsl output swing maximum value updated. ?? duty cycle minimum and maxi mum values tightened to 48/52%. ? updated table 4 on page 7. ?? phase jitter test condition and maximum value updated. ?? phase noise typical values updated. ?? additive rms jitter due to external power supply noise typical values updated. ?? footnote 3 updated limi ting the vdd to 2.5/3.3v ? added tables 5, 6, 7 for lvds, hcsl, cmos, and dual cmos operations. ? moved absolute maximum ratings table. ? added note to figure 2 clarifying cmos and dual cmos maximum frequency. ? updated figure 10 outline diagram to correct pinout. revision 1.0 to revision 1.1 ? updated table 3. ?? cmos output rise/fall time test condition updated. free datasheet http:///
SI510/511 rev. 1.1 25 n otes : free datasheet http:///
SI510/511 26 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. free datasheet http:///

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